/*
 * Copyright (c) 2012 by Paweł Lebioda <pawel.lebioda89@gmail.com>
 *
 * This file is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#define ENC28J60_CS_PORT				PORTB
#define ENC28J60_CS_DDR				 DDRB
#define ENC28J60_CS						 0
#define ENC28J60_RST_PORT	PORTE
#define ENC28J60_RST_DDR	DDRE
#define ENC28J60_RST		3
#define ENC28J60_INT_PORT	PORTE
#define ENC28J60_INT_DDR	DDRE
#define ENC28J60_INT		7

#define ENC28J60_FULL_DUPLEX	0
